The present invention relates generally to electrically erasable/programmable read only memory (EEPROM) cells. More particularly, the invention relates to modifications to active area masks to avoid tunnel dielectric window size variations and reduce cell area.
Conventional nonvolatile memory cells include EPROM, Flash and EEPROM cells. EPROM cells are electrically programmed by moving electrons onto the cell's floating gate via hot electron injection, and optically erased (removing electrons from the floating gate) by exposure of the cell to UV radiation. EEPROM cells are both electrically programmed and electrically erased by moving electrons on and off the cell's floating gate via Fowler-Nordheim tunneling. Flash cells have elements of both EPROMs and EEPROMs: they are electrically programmed by hot electron injection and electrically erased by Fowler-Nordheim tunneling. Each of these memory cells have particular applications for which they are best suited.
EEPROM cells have the advantages that they need not be exposed to UV radiation for erasure, and they do not require the cell circuitry necessary for generating fields sufficient for hot electron injection. Therefore, EEPROMs are preferred in applications where these requirements would make it impractical or impossible to use an EPROM or FLASH cell.
FIG. 1A shows a perspective view of a typical EEPROM cell. The cell 30 is a single polysilicon EEPROM cell. As such, it does not have a polysilicon control gate, but instead has a heavily doped diffusion region in the cell's substrate which is capacitively coupled to its floating gate. The cell 30 includes a single polysilicon floating gate structure 32 which performs three functions. At a first end, a tunnel extension 34 of floating gate 32 acts as an electrode in the two terminal device used for tunneling electrons from a heavily doped N.sup.+ implant 35 (also referred to as a programming Memory Diffusion or MD) through a tunnel oxide 36 (often about 80 .ANG. thick) onto floating gate structure 32. At the other end of this floating gate, a wide area plate 38 is employed as one electrode of a capacitor enabling the floating gate 32 to be raised to a high voltage (e.g., about 6 to 11 volts) by capacitively coupling a programming voltage (e.g., about 9 to 13 volts) from a second electrode 40 (heavily doped N+ silicon, referred to herein as a control gate memory diffusion) through an oxide 42 (often about 180 .ANG. thick). Between these two ends is a section of polysilicon that forms the gate 44 of a read transistor (N2).
The read transistor (N2) is connected in series with a word line transistor (N1) having a gate 46 forming part of a word line (also referred to as a row line) 31. The read and word line transistors separate a sense amp negative (-) input 48 (a source line) from a sense amp positive (+) input 50 (a drain line). Charging the floating gate 32 by tunneling electrons onto it (through tunnel oxide 36) raises the threshold voltage of the read transistor (EEPROM cell 30 is programmed). This shuts off the channel between the sense amp inputs, even when the adjacent word line transistor is turned on. Tunneling electrons off the floating gate 32 reduces the read transistor threshold voltage to negative values, effectively turning this device on (EEPROM cell 30 is erased). The word line transistor in series then controls the signal path between the two sense amp inputs 48 and 50.
The EEPROM cell is programmed or erased by charging or discharging, respectively, the floating gate 32. In order to tunnel electrons onto floating gate 32, a high voltage must be applied to the control gate memory diffusion 40. At the same time, the write column 56 is grounded and the write column transistor (N3) is turned on by, for example, selecting the row line 31 with, for example, 5 volts. The sense amp (-) input 48 can be biased from about 5 volts to a high voltage to assist tunneling electrons onto the floating gate 32. The voltage on the control gate memory diffusion 40 is capacitively coupled to the floating gate 32 as is the sense amp (-) input 48 voltage. The resulting positive voltage on floating gate 32 is sufficient to cause tunneling onto floating gate 32 through the tunnel oxide 36 where it intersects the floating gate (the tunnel oxide window 36a (shaded)), thereby programming the EEPROM cell 30.
In order to tunnel electrons off floating gate 32, a high voltage must be applied to memory diffusion 35 while ground is applied to the second heavily doped N+ implant (control gate memory diffusion) 40 which underlies and is capacitively coupled to the wide area plate 38. During this process, ground is also applied to sense amp (-) input 48. The application of high voltage to memory diffusion 35 is accomplished through a write column 56 and a write column select transistor (N3) including (i) a diffusion region 54 conductively connected to write column 56 for data input, (ii) a source/drain diffusion 58 electrically connected to memory diffusion 35, and (iii) a gate electrode 60, which is part of row line 31. When a sufficient potential is applied to the gate 60 of the write column select transistor through row line 31 while a write signal is applied through write column 56, electrons can tunnel off of the floating gate 32 to erase the EEPROM cell.
A further description of a typical EEPROM cell and its functional elements is available the publication "EPM7032 Process, Assembly, and Reliability Information Package" available from Altera Corporation of San Jose, Calif. That document is incorporated herein by reference for all purposes.
In EEPROM cells, it is very important to have a tunnel dielectric (TD) window (defined here as the cross-section of the overlapping TD and active layers) that is free of any undue window size variations that effect the cell performance. It is thus important to minimize variations in size of the TD window that may occur naturally due to processing variations. FIG. 2 shows conventional masks for the active area and tunnel dielectric which intersect to form the tunnel windows 202 and 212 for two adjacent EEPROM cells 200 and 210, respectively, of an EEPROM array on a semiconductor die 220. Referring to EEPROM cell 200 as an example, the active area mask 204 is narrowed in the region of the tunnel dielectric mask 206 in order to provide the smallest tunnel window area possible, and allow for the smallest possible control gate area (not shown), thereby reducing the EEPROM cell's overall size.
In this figure, dimension "A" is the cell height which needs to be minimized in order to achieve the smallest possible die area. Dimension "B" is the inter-cell distance which typically must be greater than some minimum value to avoid active-to-active area current leakage between adjacent cells. The extent to which the active area mask extends beyond its overlap with the TD layer mask is labeled as dimension "C". The width of the tunnel dielectric is labeled as dimension "W" of the tunnel dielectric mask 206. The width of the active area mask 204 is labeled as dimension "D." The tunnel window 202, 212 area, therefore, is defined by W.times.D. These labels are used to assist is describing active area masks throughout the present application.
Two separate effects may be responsible for TD window size variations during wafer processing. First of all, there is typically a loss of resolution in the transfer of the image of the desired feature from a mask to a photoresist, particularly in comers and tight spaces of an image. This results in a rounding of corners which generally decreases the size of the feature produced by the mask. In EEPROM processing, this phenomenon may reduce the size of the active area in the final product resulting from the active area mask. The active area is typically further reduced in size by a physical process, namely encroachment of field oxide, typically generated by thermal processes, into the mask area, particularly at comers and tight spaces of the mask. These combined optical and physical effects typically shrink the active area relative to its mask and, unless preventive measures are taken, result in encroachment of the field oxide into the tunnel window, thereby reducing its size and producing a corresponding undesirable change in the properties of the EEPROM cell.
This problem is illustrated in FIG. 3A. The desired tunnel window 300 is defined by the intersection of the active area mask 302 (having a width of dimension "D") and the tunnel dielectric mask 304. As noted above, in conventional EEPROM design, the active area mask 302 typically extends a few Angstroms beyond the edge of the tunnel dielectric mask 304 (dimension "C") to ensure that the desired area for the tunnel window 300 is obtained even in the event of an imperfect alignment of the two masks during processing. The broken line 306 represents the shape of the active area following photolithographic processing and field oxidation. As shown in the figure, the reduction in size of the actual active area relative to the active area mask 302 due to the optical and physical problems noted above results in encroachment of field oxide into the tunnel window 300. Field oxide encroachment is particularly pronounced at the corners of the active region due to two-dimensional corner effects. This makes the field oxide encroachment in the direction of the TD window 300 greater at the edges than in the center of the active area. Therefore, the edges of the active area define the limit of how large of an active layer overlap is required to avoid field oxide encroachment into the TD window.
In order to address this problem, EEPROM cells have been designed in which the active area extends beyond the tunnel dielectric towards an adjacent EEPROM cell in the array an amount sufficient such that encroachment into the region defined by the active area mask does not reach the tunnel window. This approach is illustrated in FIG. 3B. This extension ("C") of the active area mask 312 beyond the tunnel dielectric mask 314, is typically about 1 micron in length for a 0.5 micron device size EEPROM cell, and results in an active area boundary 316 that does not encroach upon the tunnel window 310. Since the distance between adjacent EEPROM cells of an array, referred to as "B" in FIG. 2, must be maintained in order to prevent charge leakage between active areas of adjacent cells (which would have a detrimental effect on array performance), the presence of the longer active area extension (C'&gt;C) means that the EEPROM cell size, referred to as A in FIG. 2, is increased. However, this increased A distance (C'+B) in the EEPROM array is undesirable since it decreases cell density on a die, requiring either a larger die for the same number of cells or that fewer cells be placed on die of a given size.
An alternative solution to the tunnel window encroachment problem is shown in FIG. 3C. This approach combines an extension (C) of the active area mask 322 beyond the dielectric mask 324 of no more than that conventionally used, however the active area mask 322 has a greater width (D'&gt;D) in the region of the tunnel window. This solution also may prevent encroachment of field oxide into the tunnel window 320 since the wider active area produced by this mask is not as susceptible to field oxide encroachment. However, it results in an increase in the area of the tunnel window 320 which also requires associated increases in size of other elements in the EEPROM array (such as the control gate), again resulting in an increased cell size and a decrease in the density of arrayed EEPROM cells for a given die area.
Therefore, it would be desirable to have an EEPROM active area mask design which would minimize the amount of active layer overlap (the extent to which the active area of a cell extends beyond the tunnel dielectric towards an adjacent cell in an array) and thus the cell size, while preventing TD window size variations due to field oxide encroachment.